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Freescale Semiconductor Advance Information
Document Number: MC34825 Rev 1.0, 8/2009
Micro-USB Interface IC Supporting Universal Charging Solution and Wired Accessories
34825
The 34825 is designed to support the Universal Charging Solution INTERFACE IC (UCS) recommended by the OMTP (Open Mobile Terminal Platform), as well as to use the same 5-pin micro or mini-USB connector for other wired accessories. The 34825 supports various types of external power supplies, such as a dedicated ac/dc adapter or a USB port, to charge the battery. It has functions built in to identify the type of the power supply, and sets low or high charging current, based on the current capability of the power supply. The 34825 monitors the power supply, and offers an up to 28 V of over-voltage protection (OVP) to the cell phone against failed power supplies. The 34825 also contains analog (PB-FREE) switches to multiplex the 5 pins, to support UART and high speed USB 98ASA00037D 20-PIN QFN data communication, mono or stereo audio headset with or without a microphone and a cord remote controller, manufacturing or researchand-development (R/D) test cables, and other accessories. ORDERING INFORMATION The 34825 monitors both the VBUS status and the resistance between the ID pin and the ground to identify the accessory being Temperature Device Package Range (TA) plugged into the mini or micro-USB connector. A high-accuracy 5-bit ADC is offered to distinguish 32 levels of ID resistance that are 3mm X 3mm MC34825EP/R2 -40C to 85C assigned to buttons in a cord remote controller or to identification (ID) UTQFN resistors of accessories. After identifying the attached accessory, the 34825 sends an interrupt signal to a host IC and the host IC can configure the analog switches via an I2C serial bus for further actions. When the accessory is detached from the cell phone, an interrupt signal is also sent to inform the host. Features * Identifies various types of power supplies to set low or high * Supports 32 ID resistance values with a high accuracy 5battery-charging-current levels bit ADC * Internal power switch to offer OVP against up to 28 V * Accessory attachment and detachment detection with an failed power supply input interrupt signal to the host IC * Supports stereo/mono headset with or without microphone * I2C interface and remote controller with pure passive components * 10 A quiescent current in Standby mode * Supports USB or UART R/D test cables * Pb-free packaging designated by suffix code EP * High speed (480 Mbps) USB 2.0 compliant
BASEBAND
GPIO I2C UART USB XCVR TEST PORT AUDIO
34825
VDDIO INT I2C_SDA I2C_SCL RXD TXD D+ DTEST1 TEST2 SPK_L SPK_R MIC VDD
CHARGER Li+
ISET OUT VBUS ID DP DM GND VBUS ID D+ DGND
USB CONNECTOR
Figure 1. 34825 Simplified Application Diagram
* This document contains certain information on a new product. Specifications and information herein are subject to change without notice.
(c) Freescale Semiconductor, Inc., 2009. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VDDIO I2C_SDA I2C_SCL
Reset I2 C Interface
OSC VBUS Detect
Internal Supplies
VDD VBUS
Gate Drive & OCP Registers and State Machine OUT
INT
Interrupt
TEST1 TEST2 RXD TXD D+ DSPK_R SPK_L MIC
Test Logic Output
ISET
UART Switches
DP DM ID
USB Switches
ID ADC
Audio Switches
VBUS GND
ID Detect
Figure 2. 34825 Simplified Internal Block Diagram
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PIN CONNECTIONS
PIN CONNECTIONS
VBUS
17
20
19
18
16 15 14 13 12 11
TRANSPARENT TOP VIEW
SPK_R SPK_L MIC D+ D-
ISET
DM
DP
ID
1 2 3 4 5 6 7 8 9 10
OUT I2C_SCL I2C_SDA INT VDD
21 GND
VDDIO
TXD
TEST2
Figure 3. 34825 Pin Connections Table 1. 34825 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section on page 13.
Pin Number 1 2 3 4 5 6 7 8 9 Pin Name SPK_R SPK_L MIC D+ DRXD TXD TEST2 VDDIO Pin Function Input Input Output IO IO Output Input Output Input Formal Name Speaker right channel Speaker left channel Microphone output D+ of the USB transceiver D- of the USB transceiver UART receiver UART transmitter TEST cable type indicator IO power supply Definition Right channel input for speaker signals Left channel input for speaker signals Microphone output to the baseband of the cell phone system D+ line of the USB transceiver D- line of the USB transceiver Receive line of the UART Transmit line of the UART Push-pull output to indicate the type of the test cable. This pin is internally pulled up to the VDDIO voltage. IO supply voltage. The VDDIO voltage is used as the reference voltage for the I2C bus signals and the pull-up voltage for the TEST2 output. This pin also functions as a hardware reset to the IC. Open-drain output to indicate the connection of a test cable IC power supply input Open-drain interrupt output Data line of the I2C interface Clock line of the I2C interface The output of the power MOSFET pass switch Open-drain output to set the charger current VBUS line of the Mini or micro-USB connector
10 11 12 13 14 15 16 17
TEST1 VDD INT I2C_SDA I2C_SCL OUT ISET VBUS
Output Input Output IO Input Output Output Input
TEST cable indicator Power supply Interrupt output I C data I2C clock Power output Charge current setting VBUS power supply
2
TEST1
RXD
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PIN CONNECTIONS
Table 1. 34825 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section on page 13.
Pin Number 18 19 20 21 Pin Name DM DP ID GND Pin Function IO IO Input Ground Formal Name D- of the USB connector D+ of the USB connector ID of the USB connector Ground Definition D- line of the mini or micro-USB connector D+ line of the mini or micro-USB connector ID pin of the mini or micro-USB connector Ground
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ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings Exceeding these ratings may cause a malfunction or permanent damage to the device.
Ratings ELECTRICAL RATINGS Input Voltage Range VBUS Pin OUT Pin SPK_L, SPK_R, DP, and DM Pins All Other Pins ESD Voltage (1) Human Body Model (HBM) for VBUS, DP, DM, ID Pins Human Body Model (HBM) for all other pins Machine Model (MM) THERMAL RATINGS Operating Temperature Ambient Junction Storage Temperature Thermal Resistance Junction-to-Case Junction-to-Ambient Peak Package Reflow Temperature During Reflow
(3), (4) (2)
Symbol
Value
Unit
V VBUS VOUT -0.3 to 28 -0.3 to 8.0 -2.0 to VDD+0.3 -0.3 to 5.5 VESD 8000 2000 200 V
C TA TJ TSTG RJC RJA TPPRT -40 to +85 150 -65 to +150 C C/W 6.0 45 Note 4 C
Notes 1. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 ), and the Machine Model (MM) (CZAP = 200 pF, RZAP = 0 ). 2. 3. 4. Device mounted on the Freescale EVB test board per JEDEC DESD51-2. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts (i.e. MC33xxxD enter 33xxx)], and review parametrics.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics Characteristics noted under conditions VDD = 3.6 V, VBUS = 5.0 V, VDDIO = 3.0 V, -40C TA 85C (see Figure 1), unless otherwise noted. Typical values noted reflect the approximate parameter means at VDD = 3.6 V and TA = 25C under nominal conditions, unless otherwise noted.
Characteristic POWER INPUT VDD Supply Voltage VDD Power-On-Reset Threshold Rising edge Hysteresis VDD Quiescent Current In Standby mode In Power Save mode In Active mode (VDD < VBUS) In Active mode (VDD > VBUS) VBUS Supply Voltage VBUS Detection Threshold Voltage Rising edge Hysteresis VBUS Supply Quiescent Current In VBUS Power mode In Active mode - Dedicated Charger In Active mode - power MOSFET is off (VBUS < VDD) VBUS Over-voltage Protection Threshold Rising edge Hysteresis VBUS Over-current Protection Threshold Triggering threshold (at onset of OTP shutoff) Over-temperature Protection Threshold Rising threshold Falling threshold VDDIO Supply Voltage SWITCH ISET Open-Drain Output MOSFET On resistance (loaded by 3.0 mA current) Leakage current (when the MOSFET is off at 5.0 V bias voltage) OUT Pin Discharge MOSFET(1) On resistance (loaded by 3.0 mA current) Leakage current (when the MOSFET is off at 5.0 V bias voltage) Power MOSFET On resistance (when VBUS = 5.0 V, TA< 50C) ROUT_DISC IOUT_OFF RPSW 200 250 0.5 100 RISETB IISET_OFF 100 0.5 VDDIO TOTP 115 1.65 130 95 145 3.6 V IBUS_OCP 1.2 1.8 2.2 A C VBUS_OVP 6.8 7.0 150 7.2 V mV IVBUS 1.2 1.2 0.5 mA mA VBUS VBUS_DET 2.65 150 2.80 V mV IVDD 2.8 9.0 16 550 850 5.0 12 22 650 1000 28 V VDD VVDDPOR 2.5 100 2.65 V mV 2.7 5.5 V Symbol Min Typ Max Unit
A
A
A
A
m
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions VDD = 3.6 V, VBUS = 5.0 V, VDDIO = 3.0 V, -40C TA 85C (see Figure 1), unless otherwise noted. Typical values noted reflect the approximate parameter means at VDD = 3.6 V and TA = 25C under nominal conditions, unless otherwise noted.
Characteristic SPK_L and SPK_R Switches On resistance (20 Hz to 470 kHz) Matching between channels On resistance flatness (from -1.2 to 1.2 V) D+ and D- Switches On resistance (0.1 Hz to 240 MHz) Matching between channels On resistance flatness (from 0.0 to 3.3 V) RXD and TXD Switches On resistance On resistance flatness (from 0.0 to 3.3V) MIC Switch On resistance (at below 2.5 V MIC bias voltage) On resistance flatness (from 1.8 to 2.3 V) Pull-down Resistors between SPK_L or SPK_R Pins to GND Signal Voltage Range SPK_L, SPK_R, D+, D-, RXD, TXD, MIC PSRR - From VDD (100 mVrms) to DP/DM Pins(4) 20 Hz to 20 kHz with 32/16 load. Total Harmonic Distortion(4) 20 Hz to 20 kHz with 32/16 load. Crosstalk between Two Channels less than 1.0MHz Off-Channel Isolation Less than 1.0 MHz POWER SUPPLY TYPE IDENTIFICATION Data Source Voltage Loaded by 0~200 A Data Source Current Data Detect Voltage Low threshold High threshold Data Sink Current DM pin is biased between 0.15 to 3.6 V DP, DM Pin Capacitance DP, DM Pin Impedance All switches are off CDP/DM RDP/DM 50 IDAT_SINK 65 100 8 135 pF M IDAT_SRC VDAT_REF 0.3 0.8 0.35 0.9 0.4 1.0 VDAT_SRC 0.5 0 0.6 0.7 200 V VA_ISO -80 VA_CT -60 dB THD 0.05 dB VA_PSRR -60 % -1.5 -0.3 1.5 3.6 dB RMIC_ON RMIC_ONFLT RPD_AUDIO 100 100 5.0 k V RUART_ON RUART_ONFLT 60 5.0 RUSB_ON RUSB_ONMCT RUSB_ONFLT 0.1 0.02 5.0 0.5 0.1 RSPK_ON RSPK_ONMCT RSPK_ONFLT 1.6 0.05 0.01 3.0 0.15 0.05 Symbol Min Typ Max Unit
A
V
A
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions VDD = 3.6 V, VBUS = 5.0 V, VDDIO = 3.0 V, -40C TA 85C (see Figure 1), unless otherwise noted. Typical values noted reflect the approximate parameter means at VDD = 3.6 V and TA = 25C under nominal conditions, unless otherwise noted.
Characteristic ID DETECTION ID_Float Threshold Detection threshold Pull-up Current Source When ADC result is 1xxxx When ADC result is 0xxxx ID Shorted to Ground Detection Detection current Detection voltage threshold LOGIC INPUT AND OUTPUT VDDIO Logic Input Level Input LOW level Input HIGH level Push-pull Logic Output (TEST2) Output HIGH level (loaded by 1.0 mA current) Output LOW level (loaded by 4.0 mA current) Open-Drain Logic Output (TEST1, INT) Output LOW level (loaded by 4.0 mA current) I2 C INTERFACE(4) VI2C_IL VI2C_IH VI2C_OL II2C_OL II2C_LEAK CI2CIN -0.2 0.7VDDIO 0 -1.0 0.3VDDIO VDDIO 0.4 4.0 1.0 8.0 V V V mA VOH VOL VODOL 0.4 0.7VDDIO 0.4 V VDDIO_IL VDDIO_IH 1.5 0.5 V V V IVCBL VVCBL_L 1.0 1.2 50 1.4 mA mV IID 1.9 30.4 2.0 32 2.1 33.6 VFLOAT 2.3 V Symbol Min Typ Max Unit
A
Low Voltage on I2C_SDA, I2C_SCL Inputs High Voltage on I C_SDA, I C_SCL Inputs Low Voltage on I2C_SDA Output Outputs Low Voltage
2 2 2
Current Load when
I2C_SDA
2
Leakage Current on I C_SDA, I C_SCL Outputs Input Capacitance of the I C_SDA, I C_SCL Pins
2 2
A
pF
Notes 1. The OUT pin discharge MOSFET is shown in Figure 15. This MOSFET will be turned on when the power MOSFET is off.
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions VDD = 3.6 V, VBUS = 5.0 V, VDDIO = 3.0 V, -40C TA 85C (see Figure 1), unless otherwise noted. Typical values noted reflect the approximate parameter means at VDD = 3.6 V and TA = 25C under nominal conditions, unless otherwise noted.
Characteristic POWER ON AND OFF DELAY VDD Power-On-Reset Timing VDD rising deglitch time VDD falling deglitch time VBUS Detection Deglitch Time (for Both Rising and Falling VBUS Over-voltage Protection Protection delay
(2)(4)
Symbol
Min
Typ
Max
Unit
ms tD2 tVDDDGT_F Edges)(4) tVBUS_DET tOVPD tOVPDGT_F 7.0 1.7 3.5 8.5 2.5 4.5 10.2 3.5 5.7 ms
s
25 2.0 -
Falling-edge deglitch time(3) VBUS Over-temperature Protection MOSFET turning off speed when OTP occurs(4) Deglitch time OSCILLATOR Oscillation Frequency SWITCHING DELAY ID Detection Delay Time after VBUS Applied (Default Value is TD = 0100) TD = 0000 TD = 0001 TD = 0010 TD = 0011 TD = 0100 ...... TD = 1111 ID DETECTION ID Float Detection Deglitch Time ID Shorted to Ground Detection Time (The Detection Current Source On Time) ADC ADC Conversion Time REMOTE CONTROL Key Press Comparator Debounce Time RESET TIMING Device Reset Time VDDIO Logic Input Timing Rising edge deglitch time Falling edge deglitch time VDDIO Reset Timing VDDIO reset pulse width
tOTP_TO tOTP_DGT
-
15
0.5 -
A/s
s
fOSC
85
100
112
kHz
tD ...... 100 200 300 400 500 ...... 1600 ...... -
ms
tID_FLOAT tVCBL
-
20 20
-
ms ms
tCONV
-
1.0
-
ms
tRMTCON_DG
-
20
-
ms
tRSTDVC tVDDIODGT_R tVDDIODGT_F tRSTVDDIO
-
10
-
s s
660 105
875 125
1130 150
s
150 -
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions VDD = 3.6 V, VBUS = 5.0 V, VDDIO = 3.0 V, -40C TA 85C (see Figure 1), unless otherwise noted. Typical values noted reflect the approximate parameter means at VDD = 3.6 V and TA = 25C under nominal conditions, unless otherwise noted.
Characteristic I2C Reset Timing I2C reset pulse width I2C_SDA/I2C_SCL concurrent low time without causing a reset I2C INTERFACE(4) SCL Clock Frequency Bus Free Time between a STOP and START Condition Hold Time Repeated START Condition Low Period of SCL Clock High Period of SCL Clock Setup Time for a Repeated START condition Data Hold Time Data Setup Time Rising Time of Both SDA and SCL Signals Falling Time of Both SDA and SCL Signals Setup Time for STOP Condition Input Deglitch Time (for Both Rising and Falling Edges) fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tDGT 1.3 0.6 1.3 0.6 0.6 0 100 20+0.1CB 20+0.1CB 0.6 55 400 300 kHz tRSTI2C tNRSTI2C 13.5 8.8 Symbol Min Typ Max Unit ms
s s s s s s
ns ns ns
s
ns
Notes 2. The protection delay is defined as the interval between VBUS voltage rising above the OVP rising threshold, and the OUT pin voltage dropping below the OVP rising threshold voltage for a VBUS ramp rate of >1.0 V/s. 3. The OVP deglitch timer is only for the falling edge threshold. 4. These parameters are not tested. They are guaranteed by design.
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ELECTRICAL CHARACTERISTICS ELECTRICAL PERFORMANCE CURVES
ELECTRICAL PERFORMANCE CURVES
SPK Switch On-Resistance ( )
MIC Switch On-Resistance ( )
2.2
Temperature =85C
90
Temperature = 85C
2.0 1.8 1.6 1.4 -1.5 -1.0 -0.5
Temperature = -40C Temperature =25C
80 70 60 50 40 1.8 1.9
Temperature = -40C Temperature = 25C
0.0
0.5
1.0
1.5
Input Voltage ( V)
Figure 4. SPK Switch On Resistance vs Input Voltage
2.0 2.1 2.2 Input Voltage ( V)
2.3
Figure 7. MIC Switch On Resistance vs Input Voltage
USB Switch On-Resistance ( )
4.0 3.5 3.0 2.5 2.0 0.0 0.5
Temperature = 85C
VDD Supply Current ( A)
4.5
9.6 9.4 9.2 9.0 8.8 8.6 2.5 3.0 3.5 4.0 4.5 VDD Voltage ( V) 5.0 5.5
Temperature = 25C
Temperature = -40C
1.0 1.5 2.0 2.5 Input Voltage ( V)
3.0
3.5
Figure 5. USB Switch On Resistance vs Input Voltage
Figure 8. VDD Supply Current vs Supply Voltage in Standby Mode
UART Switch On-Resistance ( )
45 40 35 30 25 20 0.0 0.5
Temperature = 25C Temperature = 85C
11 VDD Current ( A) 10 9 8 7
Temperature = -40C
1.0 1.5 2.0 2.5 Input Voltage ( V)
3.0
3.5
-40
-20
Figure 6. UART Switch On Resistance vs Input Voltage
0 20 40 60 Temperature ( C)
80
Figure 9. VDD Supply Current vs Temperature In Standby Mode
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ELECTRICAL CHARACTERISTICS ELECTRICAL PERFORMANCE CURVES
VBUS Supply Current ( A)
900 880 860 840 820 800 780 760 -40 -20 0 20 40 60 80
OUT Voltage (V)
9.0 7.5 6.0 4.5 3.0 1.5 0.0 0.0 1.5 3.0 4.5 6.0 VBUS Voltage ( V) 7.5 9.0
Temperature ( C)
Figure 10. VBUS Supply Current vs Temperature In VBUS Power Mode
Figure 11. OUT Voltage vs VBUS Voltage
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FUNCTIONAL DESCRIPTION INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 34825 is designed to support cell phones that adopt the micro or mini-USB connector as the sole wired interface between the cell phone and external accessories. Using the micro-USB connector for charging and USB data communication is required by the OMTP standard for the UCS. The 34825 further extends the micro-USB connector to support other accessories to eliminate all other mechanical connectors in a cell phone. The supported accessories include various audio headsets, UART connection, R/D test cables for firmware downloading, and other user defined accessories, in addition to the chargers defined in the Battery Charging Specification, Revision 1.0, from the USB Implementer's Forum and the CEA-936-A USB Carkit Specification, from the Consumer Electronics Association (CEA). The supported chargers are listed in Table 7. The 34825 offers two mechanisms to assist the identification of the accessory. The ID detection mechanism allows the cell phone to measure the ID resistor value between the ID pin and the ground with a 5-bit ADC. The VBUS detection mechanism allows the cell phone to find out the connection status between the D+ and D- pins. Together, the exact accessory can be determined. A detection flow is initiated by a change in the VBUS pin voltage or by a change in the ID pin floating status. Detaching the accessory from the micro or mini-USB connector causes the VBUS voltage or/ and the ID resistance to change. The identification flow will be initiated to confirm if an accessory is still connected. The host can also initiate the identification flow by resetting an ACTIVE bit in the register from 1 to 0. Upon the completion of the identification flow, an interrupt signal is sent to the host IC, so the host IC can take further actions. The 34825 contains switches that the host IC can control via an I2C interface. Based on the accessory, the host IC can configure the switch connections in the 34825, so that the signal paths for the USB communication, or the UART communication, or audio accessories can be established between the micro or mini-USB connector pins and the system ICs. If the accessory is a power supply, the supplied voltage is switched to the Li-ion battery charging function in the cell phone via an internal power MOSFET. The host IC controls the 34825 via the I2C serial bus. The register map in the 34825 contains status information of the device and the control bits that the host IC can access to control the 34825.
FUNCTIONAL PIN DESCRIPTION
SPEAKER RIGHT CHANNEL (SPK_R)
Right channel of the baseband speaker output.
IO POWER SUPPLY (VDDIO)
Power supply input for the logic IO interface. Generally the IO power supply voltage should be the same as the IO voltage used in the cell phone system. VDDIO is also one of the hardware reset input sources. A falling edge at this pin will reset the 34825. See Reset for more information.
SPEAKER LEFT CHANNEL (SPK_L)
Left channel of the baseband speaker output.
MICROPHONE OUTPUT (MIC)
Microphone output to the baseband.
TEST1 INDICATOR (TEST1)
Open-drain output to indicate the attachment of a test cable.
D+ OF THE USB TRANSCEIVER (D+)
D+ line of the USB transceiver.
POWER SUPPLY (VDD)
Power supply input. Bypass to ground with a 1.0 F capacitor.
D- OF THE USB TRANSCEIVER (D-)
D- line of the USB transceiver.
UART RECEIVER (RXD)
Receiver line of the UART.
INTERRUPT OUTPUT (INT)
Active low open-drain output. The INT pin sends an interrupt signal to the host IC when an interrupt event happens. The INT output returns to high voltage once all interrupt bits are read.
UART TRANSMITTER (TXD)
Transmitter line of the UART.
DATA LINE OF THE I2C INTERFACE (I2C_SDA)
Data line of the I2C interface.
TEST2 INDICATOR (TEST2)
Push-pull output to indicate the type of the connected test cable.
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FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION
I2C CLOCK (I2C_SCL)
Clock line of the I C interface. The I C_SCL input together with the I2C_SDA input forms one of the hardware reset input sources.
2 2
VBUS POWER SUPPLY (VBUS)
USB VBUS input. Bypass this pin to ground with a less than 10 nF capacitor. When the accessory is an audio kit, this pin is the microphone input to the 34825.
POWER OUTPUT (OUT)
Output of the power MOSFET in the 34825. This pin is connected to a charger input. Bypass to ground with a 1.0 F capacitor.
D- OF THE USB CONNECTOR (DM)
D- line of the mini or micro-USB connector.
D+ OF THE USB CONNECTOR (DP)
D+ line of the mini or micro-USB connector.
CHARGE CURRENT SETTING (ISET)
Open-drain output to set the charge current according to the power supply current capability.
ID OF THE USB CONNECTOR (ID)
ID pin of the mini or micro-USB connector.
GROUND (GND)
Ground.
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
I2C Interface
Internal Power Supplies
Logic & State Machine
VBUS Detection
Logic Output
Switch Array
ID ADC
ID Detection
Figure 12. 34825 Functional Internal Block Diagram
INTERNAL POWER SUPPLIES
This block contains the bias power supplies to the internal circuits. The inputs to this block include VBUS, VDD and VDDIO.
SWITCH ARRAY
The switch array consists of analog switches for UART, USB, audio signal switching and one high-voltage power MOSFET for power switching.
LOGIC AND STATE MACHINE
This block includes the state machine for accessory detection and identification, the register map, and other logic circuits.
VBUS DETECTION
This block detects whether the power supply at VBUS pin is present or removed.
I2C INTERFACE
The I2C interface block has the circuit for the I2C communication that a master device can use to access the registers in the 34825. The 34825 is a slave device.
ID DETECTION
This block contains a circuit to detect whether an ID resistor is connected to the ID pin or not.
LOGIC OUTPUT
The logic output includes open-drain or push-pull drivers for the four logic output signals, TEST1, TEST2, INT, and ISET.
ID ADC
An internal 5-bit ADC measures the resistance at the ID pin. The result is stored in the ADC Result register and sent to the Logic and State Machine block to determine what accessory is attached.
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
The 34825 has five operational modes: Power Down mode, VBUS Power mode, Standby mode, Active mode, and Power Save mode. The mode transition diagram is given in Figure 13.
Power Down
VBUS power down VBUS power up
VBUS Power
VDD > VVDDPOR VDD < VVDDPOR VDD < VVDDPOR I2C resets ACTIVE bit or detachment of accessory Active ID det or VBUS det I C or detection of no activity I2C or detection of the activity Power Save Detachment of accessory
2
VDD > VVDDPOR
Standby
Figure 13. Mode Transition Diagram
POWER DOWN MODE
The Power Down mode is when neither the VDD pin nor the VBUS pin is powered. In this mode, the IC does not respond to any accessory attachment except for a power supply. When an external power supply is plugged into the mini or micro-USB connector, the 34825 enters the VBUS Power mode.
ACTIVE MODE
The Active mode starts when an accessory is plugged into the mini or micro-USB connector while the VDD pin is powered. The 34825 identifies the accessory and interrupts the host IC for further actions. Different functions will be enabled according to the identification result, so the quiescent current in Active mode is dependent on the type of accessories. The operational mode can be changed from Active to Standby either by an accessory detachment or by resetting the ACTIVE bit to 0 through an I2C programming operation.
VBUS POWER MODE
The 34825 enters the VBUS Power mode when the VBUS pin is powered but the VDD pin is not. In the VBUS Power mode, the internal power MOSFET is turned on to power the charging function in the cell phone. The ISET pin outputs high-impedance in this mode.
POWER SAVE MODE
The Power Save mode can be enabled only for accessories with a remote controller (refer to Table 21). The 34825 enters into the Power Save mode to minimize the operating current while such an accessory is attached, but not in operation. For example, if the cell phone is not in an audio playback mode when a headset is attached, the host IC can force the 34825 to the Power Save mode via the I2C programming. The 34825 can also automatically enter into the Power Save mode when no activity is detected on the SPK_R or SPK_L pins in 10 seconds. The VDD current in the Power Save mode is slightly higher than the current in the Standby mode. The 34825 can exit the Power Save mode by an I2C programming or will exit the mode automatically when
STANDBY MODE
The Standby mode is when the VDD voltage is higher than the POR (Power-On-Reset) threshold and no accessory is attached. In this mode, only the ID detection circuit, the I2C interface, and the internal registers are powered in order to minimize the quiescent current from the VDD pin. The ID detection circuit samples the status of the ID line every 50 ms. If detecting an attachment of an accessory, the 34825 moves to the Active mode for further accessory identification.
34825
16
Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION POWER-UP
detecting audio signal activities or an accessory detachment. If the transition is caused by an accessory detachment, the 34825 moves from the Power Save mode to the Standby mode directly. Otherwise, it moves to the Active mode, and the configuration of the IC resumes to the same configuration before entering the Power Save mode.
DEVICE MODE REGISTER
The PSAVE bit, ACTIVE bit and RST bit in the Device Mode register (refer to Table 9) hold the information of the device operational mode. The RST bit, which is of R/C (read and clear) type, indicates whether a reset has occurred. The RST bit is set when a reset occurs (refer to Reset for more information). The RST bit is cleared when read by an I2C access. The ACTIVE bit and the PSAVE bit together indicate the device mode by the relationship shown in Table 5. When the device is in the VBUS Power mode, the registers are not powered up. The ACTIVE bit is a R/W (read and write) bit, it can be written by an I2C operation. When the host IC writes `0' to the ACTIVE bit, the device will be forced to the Standby mode. If an accessory is attached when the ACITVE is set to 0, the
accessory identification flow shown in Figure 14 will be restarted. The PSAVE bit is also a R/W bit. When the 34825 is configured to the Auto Power-save mode (AutoPSAVE bit is set to 1), the PSAVE bit indicates whether the 34825 is in the Power Save mode or not. When the 34825 is configured to the Manual Power-save mode (AutoPSAVE bit set to 0), the host IC can writes `1' to the PSAVE bit to force the 34825 into the Power Save mode when an Audio R/C accessory is attached. For all other accessories attachment, the 34825 does not enter the Power Save mode even the PSAVE bit is set to 1. Table 5. The Device Modes vs. the Register Bits
PSAVE 0 0 1 1 ACTIVE 0 1 1 0 MODE Standby Active Power Save Undefined
POWER-UP
The 34825 has four possible power-up scenarios depending on which of the VDD pin and the VBUS pin is powered up first. The four scenarios correspond to the following four mode transitions. 1. From Power Down to VBUS Power: the VBUS pin is powered up when VDD < VVDDPOR (VDD POR threshold) 2. From VBUS Power to Standby: VBUS is already powered when the VDD voltage rises above its POR threshold 3. From Power Down to Standby: the VDD pin is powered up when VBUS < VVBUSPOR (VBUS POR threshold) 4. From Standby to Active: the VDD pin is already powered when the VBUS voltage rises above its POR threshold
SCENARIO 2: VBUS = HIGH AND VDD IS POWERED UP (VBUS POWER MODE TO STANDBY MODE TRANSITION)
If the VBUS pin is already powered when the VDD pin is powered up, the device moves from the VBUS Power mode to the Standby mode and then quickly moves to the identification flow of the Active mode to identify the accessory, as shown in Figure 14. After the VDD pin is powered up, the 34825 starts up the internal supplies. The POR resets all register bits. The power MOSFET remains on during the reset process.
SCENARIO 3: VBUS = 0 V AND VDD IS POWERED UP (POWER DOWN MODE TO STANDBY MODE TRANSITION)
If no accessory is plugged into the micro or mini-USB connector when VDD is powered up, the 34825 moves from the Power Down mode to the Standby mode. The internal supplies are started up first, and then the whole chip is reset and is ready to accept accessories. Then when an accessory is attached, the 34825 enters the Active mode. The power MOSFET is off in this case since VBUS = 0 V.
SCENARIO 1: VDD = 0 V AND VBUS IS POWERED UP (POWER DOWN MODE TO VBUS POWER MODE TRANSITION)
If the VDD pin is not powered but the VBUS is powered up within a voltage range between the POR threshold and the OVP (over-voltage protection) threshold, the internal power MOSFET is softly turned on. The IC is in the VBUS Power mode. In this VBUS Power mode, the ISET outputs highimpedance and all registers are in the reset state. The power MOSFET remains on unless it is disabled by the over-voltage protection or the over-temperature protection block.
SCENARIO 4: VDD = HIGH AND VBUS IS POWERED UP (STANDBY TO ACTIVE MODE TRANSITION)
This is a normal VBUS detection case as shown in Figure 14. More description can be found in Power Supply Type Identification.
34825
Analog Integrated Circuit Device Data Freescale Semiconductor
17
FUNCTIONAL DEVICE OPERATION ACCESSORY IDENTIFICATION
ACCESSORY IDENTIFICATION
Accessories are categorized into two groups. Powered accessories are accessories that supply power to the VBUS pin while non-powered accessories do not. When the accessory is a powered one, the VBUS-detection mechanism will check the connection between the D+ and the D- pins as part of the power supply type identification (PSTI). A powered accessory may or may not have an ID resistor. A nonpowered accessory must have an ID resistor for the identification purpose. Accessories that have an ID resistor are grouped into three types, as listed in Table 21. 1. Test Accessories. Such accessories include two USB test cables that are powered accessories, and two UART test cables that are non-powered accessories. A test accessory has an ID resistor and four ID resistor values are reserved for them (see Table 21 for the ID resistor assignment). Two logic output pins, TEST1 and TEST2, are offered to indicate the attachment of such accessories (see Table 8). The USB or the UART switches in the IC will be turned on automatically when a test accessory is attached. 2. Accessories with a remote controller. Two accessories are offered to support remote control (RC) keys. The ID resistor values are 619 k and 1.0 M respectively, as given in Table 21. Such accessories are non-powered accessories. The 34825 monitors the ID pin continuously for key pressing when such an accessory is connected. 13 ID resistors are assigned to the remote control keys, as listed in Table 21. 3. Other accessories. The remaining ID resistor values are reserved for users to assign to their own accessories. The identification flow chart is shown in Figure 14. In the Standby mode, the 34825 monitors both the ID pin and the VBUS pin simultaneously. If an accessory is detected, the identification state machine will find out in parallel the ID resistor value and the type of the power supply (if a powered accessory is attached). When the 34825 is in the Active mode with the ACTIVE bit = 1, the host IC can force the ACTIVE bit to 0 via the I2C bus to initiate the identification state machine. The details on the identification flow for the VBUSdetection mechanism and the ID detection mechanism are described as following.
34825
18
Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION ACCESSORY IDENTIFICATION
VBUS=0V
ACTIVE = 0
ID Float
No
VBUS Applied? Yes Set VBUS_DET bit
ID Float? No Clear ID_FLOAT bit
Yes
Set DETACH bit
Set ID_FLOAT bit Yes
Set ADC RESULT
No
ID Float?
Set ID_GND bit
Yes
ID shorted to GND? No Delay TD time
Yes
ADC = 00000? No
Yes
VBUS_DET =1? No Yes Yes Key Released within 1.5s? No Set ATTACH bit No Key Released? Yes
DP->DM SHORT? Yes ID_FLOAT =1? No
No
ADC = Key Value? No
Yes
No
ADC = 1000x? Yes
ADC = 0111x? Yes
No
Yes
DM->DP SHORT? No
Turn on USB switches
Turn on UART switches
Set DP/DM _SHORT bit
Set USB_CHG bit
TEST1 pin outputs LOW
ADC = 10001 or 01111? No
Yes
TEST2 pin outputs HIGH
Set ATTACH bit
Set ACTIVE bit
Figure 14. Detailed Accessory Identification Flow Diagram
ID DETECTION
The ID detection relies on the resistance between the ID pin and the ground (RID) inside the accessory for the accessory detection and recognition. The nominal ID resistance that the 34825 supports is listed in Table 6 as well as in Table 21. The 34825 offers a 5-bit ADC for the resistance recognition and the corresponding ADC results vs. the RID are also listed in Table 6. The resistors are required to have 1% or better accuracy for the ADC to recognize successfully. A comparator monitors the ID pin for attachment and detachment detection. When no accessory is attached, the ID pin is floating. An ID_FLOAT bit in the Status register stays in the value of 1. When a resistor less than or equal to 1.0 M is connected between the ID line and the ground, the ID_FLOAT bit changes to 0. When the resistor is removed, ID_FLOAT bit returns to 1. A falling-edge of the ID_FLOAT bit represents the attachment of the accessory and the ADC is enabled to measure the ID resistance. The ADC Result register has the identification result of the RID, as given in Table 6. A rising edge of the ID_FLOAT bit represents the detachment of the accessory. The ADC results are broken into two groups. The values between `00001' to `01101' are assigned to 13 remote-control keys for the two accessories that support remote controllers, as listed in Table 21. The rest of the ADC results are assigned to various accessories. If the ADC result is one of the remote control key values in the identification flow, it is possible that the remote control key is stuck when the accessory is attached. A special Stuck Key Identification flow is designed to resolve such an issue. As shown in the Figure 14, if the stuck key is recognized but is released within 1.5s, the identification flow will return to re-detect the ID line; Otherwise, the ATTACH bit will be set and the ADC Result register has the key result. After the key is released, the 34825 will detect the ID resistance value again. If the accessory is still connected, the ATTACH bit is set again and the ADC result has the ID resistor value of the accessory.
34825
Analog Integrated Circuit Device Data Freescale Semiconductor
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FUNCTIONAL DEVICE OPERATION ACCESSORY IDENTIFICATION
When the ADC result is 00000, the resistance between the ID pin and the ground is less than 1.90 k. The ID_GND bit in the Status register indicates whether the ID pin is shorted Table 6. ADC Output vs. Resistor Values (Unit: k)
ADC Result 00000 00001 00010 00011 00100 00101 00110 00111 RID (k)
(1)
to ground or not. If the ID pin is shorted to ground with less than 30 of resistance, the ID_GND pin is set to "1".
ADC Result 01000 01001 01010 01011 01100 01101 01110 01111
RID (k) 10.03 12.03 14.46 17.26 20.5 24.07 28.7 34.0
ADC Result 10000 10001 10010 10011 10100 10101 10110 10111
RID (k) 40.2 49.9 64.9 80.6 102 121 150 200
ADC Result 11000 11001 11010 11011 11100 11101 11110 11111
RID (k) 255 301 365 442 523 619 1000
(2)
2.00 2.604 3.208 4.014 4.820 6.03 8.03
Notes 1. If the ID resistance is below 1.90 k (nominal value), the ADC result is set to 00000. 2. If the ID line is floating, the ADC result is set to 11111
POWER SUPPLY TYPE IDENTIFICATION
The 34825 supports various standard power supplies for charging the battery. The power supplies supported include those that are user defined, and the ones defined in the Battery Charging Specification, Revision 1.0, from the USB Implementer's Forum and the CEA-936-A USB Carkit Specification, from the Consumer Electronics Association. The five types of power supplies specified in the afore mentioned two specification documents are listed in Table 7. The Power Supply Type Identification (PSTI) function is offered to assist the identification of the power supply type. The PSTI state machine checks the connection status Table 7. Power Supply Type vs. Detection Result
Item # 1 2 3 4 5 VBUS_DET 1 1 1 1 1 DP/DM_SHORT 0 0 1 1 1 USB_CHG 0 1 0 0 0
between the DP and the DM pins. The state machine starts when the VBUS pin voltage rises above the VBUS detection threshold, which is indicated with an VBUS_DET bit in the status register. The state machine will find out if the DP and DM pins are shorted, indicated with the DP/DM_SHORT bit, or the connection has the characteristics of a USB charger, indicated with the USB_CHG bit. Together with the ID detection result, the power supply type can be determined. The conditions for reaching the conclusion of the five supported power supplies are listed in Table 7.
ID_FLOAT 1 1 1 0 0
ADC Result 11111 11111 11111 10111 11011
Accessory Type Standard USB Port USB Charger Dedicated Charger Carkit Charger Type 1 Carkit Charger Type 2
34825
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION OPERATION AFTER IDENTIFICATION
OPERATION AFTER IDENTIFICATION
The operation after the identification is dependent on the VDDIO voltage. The VDD voltage has to be higher than its POR threshold for the 34825 to perform the identification state machine. Once completed, the identification results are stored in the Status and the ADC Result registers and the ATTACH bit is set. If the VDDIO is not powered, the interrupt signal from the INT pin cannot be sent because the INT pin is normally pulled up to the VDDIO. The host cannot access the 34825 either via the I2C bus. Hence, no communication will occur between the 34825 and the host IC when the VDDIO is not powered. The INT signal will send an interrupt signal if the VDDIO is powered and the ATTACH bit is not masked by the ATTACH_m bit (refer to Interrupt on page 26 for more details). If the ATTACH bit is masked while the VDDIO is powered, the interrupt signal will not be sent but the host IC can still access the register map via the I2C bus. Once the host IC accesses the 34825 register map and determines the accessory type, it can manage the analog switches and other signals in the 34825 by programming the S/W Control 1 and S/W Control 2 registers. The switches are open by default except if the attached accessory is one of the four test cables listed in Table 21. More descriptions on the analog switches and the operation of the 34825 are given in the following sections.
ANALOG SWITCHES SIGNAL SWITCH ARRAY
The 34825 offers an array of analog switches for signal switching, as shown in Figure 15. Two pairs of switches (USB and UART) are for switching the UART and USB signals to the micro or mini-USB connector. Stereo audio signals can be switched from the SPK_L and the SPK_R inputs to the DP and the DM pins that are wired to the USB connector. Both the SPK_L and the SPK_R inputs are capable of passing signals of +/-1.5 V, referencing to the GND pin voltage. The SPK_L and the SPK_R pins are pulled down to ground via a 100 k resistor respectively, as shown in Figure 15. A microphone switch connects the MIC pin to the VBUS pin. All switches are controlled by bits in the S/W Control 1 and 2 registers except when the accessory attached is a test cable.
RXD
SW1
DP
TXD
SW2 SW3 SW6 SW4 SW7
DM
D+ DSPK_R SPK_L
MIC
SW5 Gate Drive
VBUS SW8 OUT SW10
ISET
SW9
Figure 15. Analog and Digital Switches
POWER MOSFET
The SW8 in Figure 15 is a power MOSFET that controls
the power flow from the VBUS input to the OUT pin. The power MOSFET serves two purposes. For the Audio accessory with microphone, the power MOSFET isolates the
34825
Analog Integrated Circuit Device Data Freescale Semiconductor
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FUNCTIONAL DEVICE OPERATION OPERATION AFTER IDENTIFICATION
VBUS pin from both the input decoupling capacitor and the input quiescent current of the charger IC connected to the OUT pin, so that the microphone signal can be connected to the VBUS pin without any interference from the OUT pin. The power MOSFET is also used as the input Over-voltage Protection (OVP) or Over-current Protection (OCP) switch for other components in the cell phone, such as the charger IC,
to allow a low voltage rated charger IC to be used for cost reduction. The power MOSFET is guaranteed to be turned on in VBUS power mode even when the VDD voltage is below VVDDPOR threshold, to ensure that the cell phone battery can be charged when the battery is fully discharged.
PROTECTION OVER-VOLTAGE PROTECTION (OVP)
The VBUS line is capable of withstanding a 28 V voltage. The 34825 protects the cell phone by turning off the internal power MOSFET when the VBUS voltage is higher than the OVP threshold. In this case, the 34825 turns off the power MOSFET within 1.0 s after the input voltage exceeds the OVP threshold, and the OVP_EN bit in the Interrupt register is set to interrupt the host IC. When the OVP event is cleared, the OVP_OTP_DIS bit in the Interrupt register is set to inform the host IC. (Constant Current) mode, regulating the output current at the OCP limit. If the OCP condition persists, the IC temperature will rise, eventually reaching the Over-TemperatureProtection (OTP) limit. The 34825 then turns off the power MOSFET and sets the OTP_EN interrupt bit in the Interrupt register to inform the host IC. The power MOSFET is turned on again when the IC temperature falls below the OTP falling temperature threshold, and the OVP_OTP_DIS bit is set. If the above case happens repeatedly 7 times, the power MOSFET will be permanently turned off until the accessory is detached or the IC is reset. The power MOSFET is turned off with a limited speed under the OTP case to prevent a high overshoot voltage at the VBUS pin.
OVER-CURRENT PROTECTION (OCP) AND OVERTEMPERATURE PROTECTION (OTP)
If the current flowing through the power MOSFET exceeds the specified OCP limit, the 34825 will operate in CC
OPERATION WITH ACCESSORIES AUDIO ACCESSORY SUPPORTING REMOTE CONTROLLER (R/C ACCESSORY)
Two ID resistors are designated for accessories with a remote controller, as listed in Table 21. A typical accessory with a remote controller is an audio headset that has a stereo speaker, a micro phone, and a remote controller, as shown in Figure 16. The five pins in the mini or micro-USB connector are assigned in Figure 16. If some components are not included in the accessory, the corresponding pins should be left floating. For example, if the microphone is not included in the stereo headset, VBUS pin should be left floating in the headset. The timing of the key pressing is shown in Figure 17. If a key is pressed for a time less than 20 ms, the 34825 ignores this key press. If the key is still pressed after 20 ms, 34825 starts a timer to count the time during which the key is pressed. There are three kinds of key press conditions according to the pressing time: error key press, short key press, and long key press. 1. Error key press: if the key pressing time is less than TKP, The 34825 ignores this key press. 2. Short key press: if the key pressing time is between TKP and TLKP, the KP bit is set to inform the host IC. The ADC result holds the key value. The INT outputs low impedance when the key is released and returns to a high impedance, due to the clearance of the KP bit when the interrupt register is read. 3. Long key press: if the key pressing time is longer than TLKP, the long key press bit LKP in the Interrupt register is set to inform the host IC. The host IC needs to respond to the key press immediately. The ADC result holds the key value. When the key is released, the long key release bit LKR in the Interrupt register is set to interrupt the host IC again. The ADC Result register still has the key value. When such a accessory is attached, the 34825 can either be forced into the Power Save mode or automatically enter into the Power Save mode. This is controlled by the AutoPSAVE bit in the Control register. When AutoPSAVE = 1, if no activity is detected at the SPK_L and SPK_R pins in 10 seconds, the 34825 enters the Power Save mode automatically to minimize the quiescent current. Upon detecting the activity in audio signal switches, the 34825 returns to the Active mode. When AutoPSAVE = 0, the host IC can control the mode of 34825 manually by setting the PSAVE bit in the Device Mode register via I2C. In the Power Save mode, the key pressing is monitored as well.
34825
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION OPERATION AFTER IDENTIFICATION
VBUS
AUDIO ACCESSORY Audio_R MIC
D+ DAudio_L ID R1 R2 R3
RN-1 ......
SEND/END GND HOLD
/
RN
Figure 16. Audio Accessory with Remote Control and Microphone
TKP 20 ms TLKP
20 ms
Key Press
20 ms
KP INT LKP LKR INT ADC Time Interrupt Register read Interrupt Register read
Interrupt Register read
Figure 17. The Remote Control Key Pressing Timing
TEST ACCESSORY
The Test Accessories listed in Table 21 are special USB cables and UART cables for test and R/D purpose. It has an ID resistance to differentiate it from a regular USB cable or UART cable. The test accessory has four ID resistance values to distinguish the test cable type. The detection result sets the TEST1 and the TEST2 outputs and turns on or off the USB switches, UART switches, and the power MOSFET automatically, as shown in the Table 8.
The TEST1 and the TEST2 outputs are High and Low respectively by default but can be changed by the TEST1 and TEST2 bits in the S/W Control 2 register, if the accessory is NOT a test cable. If the accessory is a test cable, the TEST1 outputs Low always and the TEST2 is dependent on the actual test cable. The TEST1 and TEST2 output cannot be changed by the TEST1 and the TEST2 bits in the S/W Control 2 register. The corresponding analog switches, either USB or UART switches, are turned on automatically in the case of a test cable. The TEST1, TEST2, and the switch status are summarized in Table 8.
34825
Analog Integrated Circuit Device Data Freescale Semiconductor
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FUNCTIONAL DEVICE OPERATION OPERATION AFTER IDENTIFICATION
Table 8. TEST1, TEST2, and Switch Status vs. Test Cables
Accessory Type UART test cable type 1 UART test cable type 2 USB test cable type 1 USB test cable type 2 Other accessories ADC Result 01110 01111 10000 10001 others TEST1 Output LOW LOW LOW LOW HIGH(1) TEST2 Output LOW HIGH LOW HIGH LOW(1) Auto-ON Switches UART Switches UART Switches USB Switches USB Switches Power MOSFET OFF OFF ON ON
No auto-on Switches No auto-on Switches
Notes 1. These values are default values and can be changed by the TEST1 and TEST2 bits in the S/W Control 2 register.
USB HOST (PC OR HUB)
When the attached accessory is a USB host or hub, the ID pin is floating. The power MOSFET is turned on to allow the charger to charge the battery. The ISET outputs default high impedance to limit the charging current to a lower level. The host IC can turn on the D+ and D- switches and then pull the D+ signal to high to start the USB attaching sequence.
of either 200k or 440k to distinguish the current capability of the charger. Refer to the CEA-936-A USB Carkit Specification for more information. When the attached accessory is a 5-wire carkit charger, the 34825 turns on the power MOSFET to allow the Li-ion battery charging function to start. The host can set the ISET outputting high impedance or low impedance to choose the charge current.
USB CHARGER OR DEDICATED CHARGER
When the attached accessory is a USB Charger or a Dedicated Charger, the 34825 turns on the power MOSFET to allow the charger to start. The host IC can set the ISET outputs low impedance to allow a higher charge current.
RESERVED ACCESSORY
The users can assign the reserved ID resistor values listed in Table 21 to their user specific accessories. When a user specific accessory is attached, the identification flow will identify the ID resistance and as well as the power supply type in case of a powered accessory. The ADC Result register and the Status register contain the information of the RID value and the power supply type. The baseband can read these registers to distinguish the type of the accessory for further actions.
5-WIRE CARKIT CHARGER (TYPE 1 OR TYPE 2)
A 5-wire carkit charger is a charger specified in the CEA936-A USB Carkit Specification. The 5-wire carkit charger outputs 5V to the VBUS pin, has the D+ and D- pins shorted internally, and has an ID resistor. The ID resistor has a value
DETACHING DETECTION
When either the VBUS voltage drops below the VBUS power detection threshold or the ID resistor is removed, a detaching detection flow starts. Figure 18 shows the detailed detection flow. When the DETACH bit is set, the INT outputs low voltage to inform the host IC. At the end of the detaching detection flow, the ACTIVE bit is cleared and the 34825 enters the Standby mode. A new identification flow will start if either the VBUS voltage is above its POR threshold or the ID resistor is connected.
34825
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION LOGIC CONTROL FEATURES
VBUS=5V
RID Connected
No
VBUS Removed Yes Clear VBUS_DET bit
No
ID Float Yes Set ID_FLOAT bit
Clear ATTACH bit
Set DETACH bit
Clear ACTIVE bit
Figure 18. The Detachment Detection Flow
LOGIC CONTROL FEATURES
RESET HARDWARE RESET
The 34825 has three sources for hardware resetting the IC. As the Figure 19 shows, the sources include the PowerOn-Reset caused by the rising VDD, a hardware reset caused by the VDDIO input and a hardware reset using the I2C bus lines. The Power-On-Reset is described earlier. The reset caused by the VDDIO input or by the I2C bus lines belongs to system resets. The hardware reset condition using the I2C signals is shown in Figure 20. When both the I2C_SCL and the I2C_SDA have a negative pulse with time of tRSTI2C, a hardware reset is generated. The result of the reset is same as a Power-On-Reset. The operating waveforms of the hardware reset using the VDDIO pin are shown in Figure 21. The VDDIO detection has a deglitch-time tVDDIODGT_F. A glitch on the VDDIO with duration less than the deglitch time will be ignored. If the pulse on the VDDIO lasts longer than the deglitch time, a reset from the VDDIO is detected to generate a reset signal. To effectively reset the 34825, the reset pulse from the VDDIO needs be longer than the 150 s minimum reset pulse width given in the Dynamic Electrical Characteristics table.
SOFTWARE RESET
In addition to the two hardware reset types, the system reset has another reset source, the software reset by writing `1' to the RESET bit in the Control register. The Reset bit will be cleared to `0' at once since it is of W/C type. The consequence of the software reset is the same as the hardware reset. All registers will be reset.
34825
Analog Integrated Circuit Device Data Freescale Semiconductor
25
FUNCTIONAL DEVICE OPERATION LOGIC CONTROL FEATURES
I2C_SDA I2C_SCL VDD
I2C-Bus Reset Detection + VVDDPOR Delay Time reset
VDDIO
VDDIO Reset Detection
Figure 19. Sources of Reset in 34825
8.8~13.5ms Reset
I2C_SDA I2C_SCL Reset Condition Start Condition Stop Condition
Figure 20. Hardware Reset Using the I2C Bus
tVDDIODGT_F Reset VDDIO
Figure 21. Hardware Reset Using the VDDIO Input
INTERRUPT
There are eight interrupt sources in the 34825 causing an interrupt at the INT pin to the host IC. They are accessory attachment, accessory detachment, short-key press, long key press, long-pressed key release, VBUS voltage OVP, the IC temperature OTP, and either the OVP or the OTP condition is removed. The 34825 detects each event and sets the corresponding bit in the Interrupt register. As long as the Interrupt register is set, the INT pin outputs low voltage. The Interrupt register is not writable. When the Interrupt register is read, the Interrupt register is cleared automatically. Once the Interrupt register is cleared, the INT pin returns to high voltage. An interrupt mask register is provided to mask unwanted interrupt source. When the bit of the Interrupt Mask register is set to 1, the corresponding interrupt source is blocked. The INT does not output low voltage even though this interrupt bit is set in the Interrupt register.
LOGIC OUTPUT
There are three logic outputs pins:TEST1, TEST2 and ISET. They are controlled by the register bits with the same name in the Control register if the attached accessory is NOT a test cable. The TEST2 output is a push-pull output with the
34825
voltage pulled up to the VDDIO, and the rest of them are open-drain outputs. The ISET generally is used to control the charge current level. A typical charger IC uses one external resistor to set
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION I2C SERIAL BUS INTERFACE
the charge current. By using ISET output, the charger IC can use two external resistors in parallel to set two charge current levels, as shown in Figure 27.
I2C SERIAL BUS INTERFACE
The I2C bus is enabled in the Standby, the Power Save, and the Active modes. The serial clock (SCL) and the serial data (SDA) lines must be connected to a positive supply using pull-up resistors. Internally the I2C bus voltage is referenced to the VDDIO input. The 34825 is a slave device. Maximum data rate is 400 kbps.
0
1
0
0
1
0
1
R/W
ADDRESSING AND PROTOCOL
The 7-bit address for the 34825 is 0100101, as shown in Figure 22.
Figure 22. I2C Slave Address The following three figures show three I2C-bus transaction protocols. The Word Address is an 8-bit register address in the 34825.
Figure 23. Master Transmits to Slave (Write Mode)
Figure 24. Master Reads After Setting Word Address (Write Word Address and then Read Data)
34825
Analog Integrated Circuit Device Data Freescale Semiconductor
27
FUNCTIONAL DEVICE OPERATION REGISTER MAP
Figure 25. Master Reads Slave Immediately after First Byte (Read Mode)
REGISTER MAP
Table 9. Register Map
Addr
83H 85H 87H 88H 93H 94H A0H A1H A2H A3H
Register
Interrupt Interrupt Mask ADC Result Timing Set S/W Control 1 S/W Control 2 Status Control Time Delay Device Mode
Type
R/C R/W R R/W R/W R/W R R/W R/W R/W
Reset Value
00000000
Bit 7
OVP_OTP_DIS
Bit 6
OTP_EN OTP_EN_m Reserved Key Press Reserved
Bit 5
OVP_EN OVP_EN_m Reserved
Bit 4
LKR LKR_m
Bit 3
LKP LKP_m
Bit 2
KP KP_m ADC Value
Bit 1
DETACH DETACH_m
Bit 0
ATTACH ATTACH_m
00000000 OVP_OTP_DIS_m 00011111 00000000 00000001 00000100 0x000xxx 011000x0 10010100 00000001 Reserved Reserved Reserved Reserved Reserved Reserved
Long Key Press DP/DM Switching Reserved USB_CHG ISETB DP/DM_SHORT Reserved Reserved Reserved Reserved PSAVE TEST2 ID_GND Reserved TEST1 ID_FLOAT RESET TD ACTIVE RST VBUS Switching Reserved VBUS_DET Reserved ADC_STATUS Reserved
Reserved FET_STATUS Reserved Reserved Reserved
AutoPSAVE Reserved Reserved
Table 10. Interrupt Register
Bit 0 1 2 3 4 5 6 7 Mode R/C R/C R/C R/C R/C R/C R/C R/C Symbol ATTACH DETACH KP LKP LKR OVP_EN OTP_EN OVP_OTP_DIS Reset 0 0 0 0 0 0 0 0 1: accessory attached 1: accessory detached 1: remote controller short key is pressed 1: remote controller long key is pressed 1: remote controller long key is released 1: VBUS voltage higher than the OVP threshold 1: The temperature of 34825 is above the OTP threshold 1: OVP or OTP event is removed Description Notes
Table 11. Interrupt Mask Register
Bit 0 1 2 3 4 Mode R/W R/W R/W R/W R/W Symbol ATTACH_m DETACH_m KP_m LKP_m LKR_m Reset 0 0 0 0 0 1: interrupt disabled 1: interrupt disabled 1: interrupt disabled 1: interrupt disabled 1: interrupt disabled Description Notes
34825
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION REGISTER MAP
Table 11. Interrupt Mask Register
Bit 5 6 7 Mode R/W R/W R/W Symbol OVP_EN_m OTP_EN_m OVP_OTP_DIS_m Reset 0 0 0 1: interrupt disabled 1: interrupt disabled 1: interrupt disabled Description Notes
Table 12. ADC Result Register
Bit 4-0 7-5 Mode R R Symbol ADC Result Reserved Reset 11111 000 ADC Result of the ID resistor Description Notes
Table 13. Timing Set Register
Bit 3-0 Mode R/W Symbol Long Key Press Reset 0000 Long key press duration 0000: 300 ms 0001: 400 ms 0010: 500 ms ...... 7-4 R/W Key Press 0000 Normal key press duration 0000: 100 ms 0001: 200 ms 0010: 300 ms ...... Description Notes
Table 14. Timing Table
Setting Value 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Key Press 100 ms 200 ms 300 ms 400 ms 500 ms 600 ms 700 ms 800 ms 900 ms 1000 ms Long Key Press 300 ms 400 ms 500 ms 600 ms 700 ms 800 ms 900 ms 1000 ms 1100 ms 1200 ms 1300 ms 1400 ms 1500 ms -
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FUNCTIONAL DEVICE OPERATION REGISTER MAP
Table 15. S/W Control Register 1
Bit 1-0 Mode R/W Symbol VBUS Switching Reset 01 Description VBUS line switching configuration 00: open all switches connected to the VBUS line. 01: internal power MOSFET on 10: VBUS connected to MIC 11: open all switches connected to the VBUS line. 4-2 R/W DP/DM Switching 000 DP/DM line switching configuration 000: open all switches 001: DP connected to D+, DM connected to D010: DP connected to SPK_R, DM connected to SPK_L 011: DP connected to RxD, DM connected to TXD Others: open all switches connected to the DP pin and DM pin 7-5 R Reserved 000 Notes
Table 16. S/W Control Register 2
Bit 1-0 2 Mode R/W R/W Symbol reserved TEST1 Reset 00 1 TEST1 output 0: low-impedance 1: high-impedance 3 R/W TEST2 0 TEST2 output 0: low voltage 1: high voltage 4 R/W ISETB 0 ISET output 0: high-impedance 1: low-impedance 7-5 R/W Reserved 000 Description Notes
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FUNCTIONAL DEVICE OPERATION REGISTER MAP
Table 17. Status Register
Bit 0 Mode R Symbol ADC_Status Reset x ADC conversion status 1: ADC conversion completed 0: ADC in progress 1 R VBUS_DET x VBUS voltage is higher than the POR 0: no 1: yes 2 R ID_FLOAT x ID line is floating 0: no 1: yes 3 R ID_GND 0 ID pin is shorted to ground 0: no 1: yes 4 R DP/DM_SHORT 0 DP/DM shorted 0: no 1: yes 5 R USB_CHG 0 A USB charger is connected 0: no 1: yes 6 R FET_STATUS x The on/off status of the power MOSFET 0: off 1: on 7 R Reserved 0 Description Notes
Table 18. Control Register
Bit 0 1 2 Mode R/W R/W W/C Symbol Reserved Reserved RESET Reset 0 x 0 Soft reset. When written to 1, the IC is reset. Once the reset is complete, the RST bit is set and the RESET bit is cleared automatically. 1: to soft reset the IC 3 4 5 R/W R/W R/W Reserved Reserved AutoPSAVE 0 0 1 Automatic Power Save mode detection control 0: disable automatic Power Save mode detection. Device can enter Power Save mode via the I2C 1: enable automatic Power Save mode detection. 6 7 R/W R/W Reserved Reserved 1 0 Description Notes
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FUNCTIONAL DEVICE OPERATION REGISTER MAP
Table 19. Time Delay Register
Bit 3-0 Mode R/W Symbol TD Reset 0100 Description Time delay to start the powered accessory identification flow after detecting the VBUS voltage 0000: 100 ms 0001: 200 ms 0010: 300 ms 0011: 400 ms 0100: 500 ms ...... 1111:1600 ms 7-4 R/W Reserved 1001 Notes
Table 20. Device Mode Register
Bit 0 Mode R/C Symbol RST Reset 1 Description This bit indicates if a chip reset has occurred. This bit will be cleared once being read. 0: no. 1: Yes. 1 R/W ACTIVE 0 Indicate either the device is in Active mode 0: Standby 1: Active 2 R/W PSAVE 0 To indicate either the device is in Power Save mode 0: no 1: yes 7-3 Reserved 00000 Notes
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TYPICAL APPLICATIONS APPLICATION INFORMATION
TYPICAL APPLICATIONS
APPLICATION INFORMATION
ID RESISTANCE VALUE ASSIGNMENT
The ID resistors used with the 34825 are standard 1% resistors. Table 21 lists the complete 32 ID resistor assignment. The ones with the Assigned Functions filled are the ones that are already used with special functions. The ones reserved can be assigned to other functions. Table 21. ID Resistance Assignment (Unit: k)
Item# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ADC Result 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 ID Resistance <1.9 2.0 2.604 3.208 4.014 4.820 6.03 8.03 10.03 12.03 14.46 17.26 20.5 24.07 28.7 34.0 40.2 49.9 64.9 80.6 102 121 150 200 255 301 365 442 523 Assignment Reserved S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 UART Test Cable 1 UART Test Cable 2 USB Test Cable 1 USB Test Cable 2 Reserved Reserved Reserved Reserved Reserved Carkit Charger Type 1 Reserved Reserved Reserved Carkit Charger Type 2 Reserved
Table 21. ID Resistance Assignment (Unit: k)
Item# 29 30 31 ADC Result 11101 11110 11111 ID Resistance 619 1000 Assignment R/C Accessory 1 R/C Accessory 2 ID float
The remote control architecture is illustrated in Figure 26. The recommended resistors for the remote control resistor network are given in Table 22. Table 22. Remote Control Resistor Values (Unit: k)
Resistor R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 Standard Value 2.0 0.604 0.604 0.806 0.806 1.21 2.0 2.0 2.0 2.43 2.8 3.24 3.57 590/976 ID Resistance 2.0 2.604 3.208 4.014 4.82 6.03 8.03 10.03 12.03 14.46 17.26 20.5 24.07 614/1000
ID
R1
R2
R3 ......
R13
S0 GND HOLD
S1
S2
S12
R14
Figure 26. Remote Control Architecture
DECOUPLING CAPACITOR
Decoupling capacitors are required at all power supply input and output pins. For the VDD pin, a X5R capacitor of 1.0 F is recommended. For VBUS pin, because it also acts as the microphone input, the decoupling capacitance at VBUS pin must be carefully considered. Assuming the voice band is 3.4 kHz and the pull-up resistance for the microphone is 2k, the decoupling capacitance at the VBUS pin should
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TYPICAL APPLICATIONS TYPICAL APPLICATIONS
be less than 22 nF. A 4.7 nF X5R capacitor is recommended for the typical application. The OUT pin requires a 1.0 F
decoupling capacitor; a 0.01 F capacitance is enough for the VDDIO pin.
TYPICAL APPLICATIONS
INTERFACE CIRCUIT IN A CELL PHONE
When the 34825 is used in a cell phone. The typical circuit is shown in the Figure 27. The I2C bus need two pull-up resistors. Typically they are 4.7 k. When the audio outputs
VDDIO 2x4.7 k Baseband
of the cell phone baseband or application processor are direct drive signals, the audio signals can be connected to the corresponding pins of 34825 directly. Otherwise these signals need DC-blocking capacitors to remove the DC level.
VDD
IC GPIO UART USB Xcvr Test Interface
2
I C_SDA I2C_SCL INT VDDIO RxD TxD D+ DTEST1 TEST2 ID DP DM GND MIC * * SPK_L SPK_R ISET OUT VBUS
2
1.0 F
Li+
MC34673
1.0 F
12 k
9.1 k
VBUS 4.7 nF
VAIO 2k
0.1 F
ID D+ DGND SHLD
Audio
* : For direct-drive audio output, these DC blocking capacitors are not needed
Figure 27. Interface Circuit in a Cell Phone System
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TYPICAL APPLICATIONS PACKAGE DIMENSIONS
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the "98A" listed below.
EP SUFFIX 20 LD. QFN 98ASA00037D REVISION O
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TYPICAL APPLICATIONS PACKAGE DIMENSIONS
EP SUFFIX 20 LD. QFN 98ASA00037D REVISION O
34825
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Analog Integrated Circuit Device Data Freescale Semiconductor
PACKAGE DIMENSIONS
EP SUFFIX 20 LD. QFN 98ASA00037D REVISION O
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Analog Integrated Circuit Device Data Freescale Semiconductor
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REVISION HISTORY
REVISION HISTORY
REVISION 1.0
DATE 8/2009
DESCRIPTION OF CHANGES * Initial Release
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Analog Integrated Circuit Device Data Freescale Semiconductor
How to Reach Us:
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Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part.
FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc. 2009. All rights reserved. MC34825 Rev 1.0 8/2009

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